1. Field of the Invention
The present invention relates to a reassembly buffer device for controlling data transmission in an ATM network, a device for circuit emulation service, and an ATM communication system.
2. Description of the Related Arts
A circuit emulation service (CES) device for use in fixed rate data transmission control in an Asynchronous Transfer Mode (ATM) network generally has a segmentation function and a reassembly function.
The segmentation function refers to a function of converting a Synchronous Transfer Mode (STM) data stream to ATM cells in accordance with ATM Adaptation Layer 1 (AAL1), and the reassembly function is another function possessed by the AAL1 to restore the STM data stream from ATM cells.
FIG. 1 illustrates an exemplary configuration of an ATM communication system which is equipped with the CES device.
As illustrated in FIG. 1, CES device 110 is installed between ATM network 120 and STM network 130.
CES device 110 has segmentation means 111 for implementing the segmentation function, and reassembly means 112 (reassembly buffer means) for implementing the reassembly function.
With the foregoing configuration, CES device 110 provided in ATM communication system 100 can convert an STM data stream from STM network 130 to ATM cells in accordance with AAL1 in segmentation means 111 and transmits the ATM cells to ATM network 120 at CBR (Constant Bit Rate).
Then, CES device 110 can terminate ATM cells from ATM network 120 at reassembly means 112 in accordance with AAL1 to restore an STM data stream.
In the configuration as illustrated in FIG. 1, when a sending STM network and a receiving STM network are placed in a plesiochronous environment such as an international communication, an adaptive clock method must be used to transfer clock information and restore a clock on the reception side.
FIG. 2 illustrates an exemplary configuration of a conventional reassembly means for implementing the adaptive clock method.
As illustrated in FIG. 2, conventional reassembly means 112 accumulates AAL1 payload data in reassembly buffer memory 112-1, controls the frequency of a local clock based on a level to which reassembly buffer memory 112-1 is filled, and drives PLO 112-2 based on the controlled local clock to read ATM cells, thereby implementing the adaptive clock method.
As appreciated, reassembly buffer memory 112-1 is provided for absorbing delays and fluctuations in ATM network 120.
The frequency of the local clock is controlled by driving PLO (Phase Locked Oscillator) 112-2 for use in supplying the local clock such that the filling level of reassembly buffer memory 112-1 is regulated substantially at the center thereof.
Also, the filling level of reassembly buffer memory 112-1 can be maintained between two limit values for preventing reassembly buffer memory 112-1 from overflowing and underflowing.
In recent years, a variety of improvements have been proposed on STM data stream synchronous transmission approaches in CES devices using the adaptive clock method.
For example, an example of the prior art for generating a synchronization clock from an ATM cell stream using the adaptive clock method is disclosed in Japanese Patent Application Laid-open No. Hei 7-46257 (46257/95), entitled “Adaptive Clock Restore Method and Apparatus.”
The adaptive clock restore method and apparatus disclosed in this official gazette, as illustrated in FIG. 3, comprise CES IWF (CBR Emulation Service InterWorking Function) installed between ATM network 120 for receiving STM data streams from a plurality of transmission sources a–n and a synchronization based terminal, not shown represented by TDM (Time Division Multiplexer) or the like as CES device 110 for terminating the ATM protocol to convert data between TDM and ATM.
This CES IWF monitors reassembly buffer memory 112-1 (a FIFO buffer is used in a conventional adaptive clock restore method and apparatus) for data accumulated therein, controls the frequency of a read clock in accordance with a difference of the accumulated data from a predetermined target value and reads data from reassembly buffer memory 112-1 based on the controlled read clock.
Also, in the network configuration having the CES IWF one communication connection (CBR virtual circuit) is set between synchronization based terminals.
Therefore, a synchronization clock can be restored from an asynchronous packet stream such as an ATM cell stream.
Another example of prior art CES device for implementing the adaptive clock method is disclosed in Japanese Patent No. 2842379 entitled “Synchronization Control Apparatus and Synchronization Control Method.”
As illustrated in FIG. 4, the synchronization control apparatus and synchronization control method disclosed in this patent comprise reassembly buffer memory 112-1 (memory means); PLO 112-2 (correcting means) for controlling the frequency of a read clock based on the amount of data accumulated in this reassembly buffer memory 112-1; and the like. These components are provided for each time slot.
Thus, a connection is established between an ATM network and synchronization based terminals for each time slot, so that when a free time slot exists within a data frame of a synchronization based terminal on the reception side data from a synchronization based terminal on the other path can be accommodated in the free time slot. In addition, a plurality of paths can be established between the same synchronization based terminals.
However, the conventional adaptive clock restore method and apparatus have a problem that the read clock cannot be correctly restored due to an anomalous amount of accumulated data from a connection between each sending side and the receiving side, caused by a change in the state of the connection, when a single read clock is requested to restored from a plurality of data transmission sources, as is the case with a channelized line.
Specifically, if one of operating connections disclosed or failed data received from this connection cannot be ensured, resulting in a failure in ensuring the amount of received data accumulated in the reassembly buffer memory, and even the read clock which is restored based on the amount of accumulated data.
Therefore, even if other connections are normal, the convent ional adaptive clock restore method and apparatus cannot ensure data sent to all outgoing lines, including data in these normal connections.
Also, the conventional synchronization control apparatus and synchronization control method comprise a buffer memory, PLO and the like for each connection to control data read from the reassembly buffer memory based on the amount of data from each connection accumulated in the reassembly buffer memory.
This control policy requires a number of circuits for read-out equal to the number of connections, in spite of a single outgoing line causing an increase in circuit scale.